ASIC Verification - Team Lead

Microsoft•Santa Clara, CA

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission. The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives DPU Silicon engineers have the opportunity to work on a wide range of exciting technologies including PCIe, DDR, processors and custom accelerators.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Nice To Haves

Experience working with large verification projects, including cluster/subsystem and fullchip environments.
Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion.
Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements.
Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
Comfortable and experienced with AI based tools to accelerate productivity.
Experience with coverage-driven verification, functional coverage, and code coverage analysis.
Execute simulations using industry-standard tools/languages (e.g., SystemVerilog, Perl, C/C++, Assembly, UVM, VCS, Simvision) and analyze results to identify and resolve design issues.
Understanding of digital design, computer architecture (ARM, RISC-V, MIPS), and verification methodologies.
Familiarity with AMBA protocols (AXI, AHB, APB), ethernet and PCIE interfaces
Collaborate with cross-functional teams to define verification scope, coverage goals, and debug strategies.
Document verification methodologies, test results, and debug findings for internal reviews and compliance.
Participate in design reviews, contribute to architecture discussions, and support post-silicon validation efforts.
Debugging skills and ability to work independently in a fast-paced environment.

Responsibilities

Improves verification efficiency through new and updated methodologies or tools. Defines verification strategies and test plans.
Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels. Drives the development of verification environments, runs, and debugs simulations to drive quality. Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff. Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals.
Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs. Determines type of performance model needed and appropriate model fidelity. Leads development of the performance model. Organizes analysis of workload information to identify performance bottlenecks. Collaborates across functions to propose architectural/microarchitectural changes and provide quantitative justification. Leads verification of correlation of system on chip (SoC) performance models to RTL implementation.
Drives development of tools/scripts and guides team to implement silicon debug tools and capabilities, such as crash dumps, register dumps, triggers and tracing, and closed chassis/remote debug.
Develops comprehensive, full-chip validation strategy, requirements, environments, tools, and methodologies, including debug board, hardware/software, and lab requirements. Organizes creation of content to run on both bare metal and operating system (OS) environments (e.g., synthetic system on chip (SoC) validation targeting Core, Coherency, Memory, Input/Output (I/O), Accelerators, Security).

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