ASIC RTL Integration and Netlisting Engineer - New College Grad 2026

NVIDIA • Santa Clara, CA

1d

About The Position

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. We are now looking for a motivated ASIC RTL Integration and Netlisting Engineer to join our dynamic and growing team. If you want to challenge yourself and be a part of something great, join us today! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing! More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities which are hard to tackle, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human inventiveness and intelligence.

Requirements

• Bachelor's degree or Master's in Electrical or Computer Engineering (or equivalent experience).
• Strong understanding of RTL and RTL hierarchy and associated infrastructures.
• Strong understanding of VLSI design.
• Solid understanding of logic synthesis and associated verification such as equivalence checking.
• Knowledge of gate level netlist verification and completeness with respect to power, testability, etc.
• Hands-on experience and solid understanding of industry standard EDA tools.

Nice To Haves

• Understanding in clock-domains, async interfaces and MTBF analysis.
• Understanding of Physical Design flows, design constraints, timing and power convergence.
• Proficiency in programming/scripting languages (Python, TCL etc) and/or AI tools (Cursor, Copilot, etc).

Responsibilities

• Drive physical design integration and implementation of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level.
• Drive RTL integration, synthesis, along with all physical netlist deliverables across various milestones.
• Drive formal equivalence checking, netlist quality checks, asynchronous checking including clock domain crossing checks and MTBF analysis, etc.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level