ASIC/RTL Design Engineer

Advanced Micro Devices, Inc • San Jose, CA

8h

About The Position

AMD is looking for a Senior ASIC/RTL Design Engineer to contribute to the development of large SoCs, featuring multiple physical blocks and complex timing constraints. The candidate's responsibilities will include RTL ownership and integration, building and verifying timing constraints for intricate SoC designs. This role demands a combination of SDC expertise, EDA tool proficiency, and TCL-based scripting abilities. The candidate should possess extensive experience in SDC development and debugging, be familiar with enhancing various RTL quality metrics for complex, hierarchical designs, and be able to automate these processes for increased efficiency. Proficiency in both front-end (RTL) processes and back-end (Synthesis and P&R) processes is preferred.
THE PERSON:
The ideal candidate demonstrates high energy, excellent written and verbal communication skills, and a structured, organized approach to work. They are collaborative and strongly focused on achieving team and organizational goals.

Requirements

• Experience with SoC designs that includes RTL design and integration.
• Worked with EDA tools that enable RTL quality checks.
• Hands on experience in building the timing constraints for IPs, blocks and Full-chip implementation in both flat/hierarchical flows.
• Experience with analyzing the timing reports and identifying both the design and constraints related issues.
• Ability to multitask, grasp new flows/tools/ideas.
• Experience in improving the methodologies.
• Strong analytical and problem-solving skills.
• Bachelor’s or Master's degree in Electrical Engineering or Computer Engineering

Nice To Haves

• Preferred EDA tool experience: Synopsys Design Compiler/Primetime, Spyglass, Fishtail etc.
• Prior experience developing complex TCL scripts in Synopsys Design Compiler (DC) and PrimeTime (PT).
• Writing custom TCL QC and QoR checks using DC/PT object attributes queries and filters.

Responsibilities

• Responsible for RTL design and integration.
• The candidate is expected to contribute to all aspects of SoC design including chip definition, architecture development and modeling, development of micro-architectural specification, conversion of micro-architectural specifications to logic implementation, verification, emulation, debug, synthesis and timing closure.
• Responsible for the development of complex multi-mode / multi-corner timing constraints that are compatible for RTL and signoff.
• Lead the effort to maintain RTL quality metrics in complex, hierarchical designs, while automating the process for increased efficiency.
• Implement the pre-route timing checks and QoR clean up to eliminate timing constraints issues and ensure a quality handoff for STA (static timing analysis) checks.
• Collaborate with CAD on the development of pre-production synthesis (Design Compiler) and STA (Primetime) work flows.
• Require a blend of SDC expertise, proficiency in EDA tools, and Tcl based scripting abilities (in both EDA environment and standalone Linux Tcl shell scripts).
• Continuously review and identify areas for process improvements and early issue detection during the design phase.

Benefits

• AMD benefits at a glance.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees