Seeking a highly experienced ASIC Physical Design Lead to drive the implementation of complex SoC designs from RTL handoff through tapeout. The ideal candidate has 10+ years of hands-on experience in advanced node physical implementation, proven ownership of multiple successful tapeouts, and the ability to lead both technically and organizationally. In this role, you will partner closely with Architecture, RTL Design, Verification, DFT, and Power teams to deliver high-performance, power-efficient silicon across cutting edge technology nodes.