ASIC Packet Processing Architect

ZP Group•San Jose, CA

78d•$280,000 - $300,000•Onsite

About The Position

Piper Companies is seeking a Packet Processor Architect to join a fast-growing innovator in AI infrastructure, for an onsite permanent position in Saratoga, CA. The Packet Processor Architect will design and lead the development of high-performance packet processing hardware that powers fast, intelligent data movement across complex network systems.

Requirements

15+ years of experience in networking or data-path ASIC architecture and design, with a proven track record in architecting packet-processing engines in high-throughput ASICs or SoCs
Design and define microarchitecture for packet processing pipelines, including programmable datapaths, parser/deparser logic, hash function optimization, and efficient lookup structures
Lead performance modeling and architectural trade-off analyses, balancing throughput, latency, area, and power across the ASIC lifecycle
Oversee system-level integration of high-speed interfaces and IP blocks (e.g., PCIe, DMA, SerDes), ensuring alignment with physical design constraints and product goals
Troubleshoot and resolve complex packet processing issues, applying deep protocol knowledge and cross-functional collaboration to deliver robust networking solutions

Responsibilities

Architect scalable packet processing pipelines including classification, switching, routing, tunneling protocols (e.g., VxLAN, GRE), and congestion control features for high-performance networking ASICs
Translate high-level requirements and use cases into detailed architectural and functional specifications while collaborating across hardware, firmware, and software teams
Lead design validation and modeling of packet flow behavior across L2-L4, optimizing for throughput, latency, area, and power efficiency
Drive IP integration and architectural decisions, including lookup optimizations, memory architecture, resource allocation, and support for programmable datapaths
Support full development lifecycle, from design reviews to post-silicon tuning, performance debugging, and protocol compliance validation