ASIC Intern

Etched•San Jose, CA

2d•Onsite

About The Position

Etched is building the world’s first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. The role We are looking for interns across RTL Design, Design Verification, or Physical Design to join our team. As an RTL Intern at Etched, you will help design microarchitecture and implement logic in verilog. You will work with cutting-edge machine learning architectures, contribute to RTL block development, and participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback. You do not necessarily need prior ML/AI hardware experience; just the ability to learn quickly in a fast-paced, high-autonomy environment. As a Design Verification intern, you will ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. As a Physical Design intern, you will be responsible for realizing our front-end designs in silicon, helping Etched to improve iteration speed to final signoff. You will assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions.

Requirements

Progress towards a Bachelor’s, Master’s, or PhD degree in electrical engineering, computer engineering, or a related field
Familiarity with high-speed digital logic
Exposure to ASIC or SoC design concepts
Familiarity with SystemVerilog, UVM, or Python
Familiarity with verification work and writing test benches
Familiarity with physical design flows and tooling
Are able to learn quickly about transformers and other aspects of modern artificial intelligence

Nice To Haves

Familiarity with transformer models and machine learning
Familiarity with numerical representations and functions (RTL)
Familiarity with clocking and reset schemes (RTL/PD)
UVM or formal verification experience (DV)
Ability to program with Python or another scripting language

Responsibilities

Design microarchitecture and implement logic in verilog
Contribute to RTL block development
Participate in the full design cycle—from microarchitecture discussions to synthesis and timing feedback
Ensure the custom IPs powering our chips — including systolic arrays, DMA engines, and NoCs — are robust, high-performance, and silicon-ready
Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack
Assist in developing and running Physical Design flows to synthesize blocks, automate final design checks, and advise RTL design decisions