ASIC Implementation Engineer

AMDSanta Clara, CA
112d

About The Position

At AMD, we care deeply about transforming lives with our technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming, and embedded systems. Underpinning our mission is the AMD culture, where we push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. We are looking for a dynamic, energetic candidate to join our NTSG - Network Technology Solutions Group team, working with our AMD Pensando DPU product. We are seeking a highly motivated and experienced ASIC Implementation Engineer to lead the implementation of complex ASIC designs, from synthesis to tape-out, while collaborating closely with architects, designers, and physical design teams.

Requirements

  • Strong experience in Synthesis.
  • Experience with LINT, Clock domain crossing, and reset domain crossing signoff.
  • Proficiency in Logic equivalency checks.
  • Knowledge of front-end ASIC flows.
  • Experience in communicating across functional internal teams and vendors.
  • Scripting and programming experience using Perl, TCL, Python, Cshell, and Make.
  • Experience with SOC design integration and Front-end implementation.
  • Knowledge of Timing/physical libraries and memories.
  • Familiarity with Design Compiler, Fusion Compiler, Spyglass, Zero-in, Primetime, Formality, and Conformal LEC.

Responsibilities

  • Run Logic/Physical synthesis using advanced techniques to generate netlists with optimized power, performance, and area.
  • Perform logic equivalency checks for blocks/chip and analyze/debug the results.
  • Conduct Flat and Hierarchical clock domain crossing and collaborate with designers to analyze complex clock domain crossings.
  • Execute Flat and Hierarchical reset domain crossing checks and understand reset architecture by working closely with designers.
  • Perform RTL Lint and work with designers to create waivers.
  • Create timing constraints for synthesis.
  • Develop automation scripts and methodologies for all Front-end tools including LINT, CDC, RDC, SYN, LEC.

Benefits

  • AMD benefits at a glance.
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