Are you ready to take your engineering career to the next level and be a part of something truly extraordinary? Join our trailblazing team in the Philadelphia metro area, where you'll dive into the thrilling world of high-assurance encryption products and programs that are pivotal to national defense. Our rapidly expanding business is not just growing—it's exploding with opportunities for innovation and impact in network and tactical encryption products and systems. Imagine working on the front lines of technology, developing state-of-the-art solutions that safeguard our nation's security. You'll collaborate with some of the brightest minds in the industry, in an environment that champions creativity and excellence. If you're passionate about tackling complex challenges and eager to contribute to groundbreaking projects that make a real difference to our warfighters, citizens, and nation; this is your chance to shine. Apply now and embark on this exhilarating journey with us, shaping the future of defense technology! Job Description: Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will architect, implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP protocols. L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This is a key, high impact role in the organization to ensure robust quality and delivery of communication products for National Security.