ASIC & FPGA Design Engineer Senior

Lockheed Martin•Orlando, FL

12h•Hybrid

About The Position

You will be the Senior ASIC & FPGA Design Engineer for the Laser Weapon System (LWS) Turret Closing team. Our team is responsible for delivering high performance, low latency FPGA based closed loop motor control solutions that enable rapid, precise turret positioning for next generation directed energy weapons. What You Will Be Doing As the Senior ASIC & FPGA Design Engineer you will lead the end to end development of the FPGA motor control hardware, translating system level performance, safety and reliability requirements into a robust architecture, driving verification, hardware in the loop testing and integration, and shepherding the design from concept through production release.

Requirements

MUST BE A U.S. CITIZEN - This position is located at a facility that requires special access. The selected candidate must be able to obtain a secret clearance. A Secret clearance with investigation or CV date within 5 years is required to start.
Bachelor’s degree or higher in Electrical or Computer Engineering.
Relevant experience with FPGA design and simulation verification.
Proficient with Xilinx/AMD (Vitis, Vivado) and MicroSemi/Microchip FPGA families, including UltraScale methodology, HLS, IP, and debugging tools (ChipScope, Synplify, VCS, NCSim).
Strong communication, collaboration, and presentation abilities.
Expertise in HDL (Verilog, SystemVerilog, VHDL) and embedded C/C++ development; MATLAB/Simulink modeling.
Protocol knowledge: AXI, Ethernet, TCP/IP, PCIe, and serial interfaces.
Networking proficiency with Ethernet switches/routers/firewalls and debugging tools (tcpdump, Wireshark).
Linux/UNIX experience with scripting in BASH, csh, Perl, and/or Python.
Controls and digital loop‑closure applications knowledge.

Nice To Haves

UVM methodology and HDL Coder integration.
Implementation of NSA‑type algorithms (e.g., AES, counter‑mode).
Aerospace design techniques and Lockheed Martin MFC process experience.
Configuration management expertise, preferably GitLab.
Competence operating high‑speed test equipment (oscilloscopes, spectrum analyzers, power meters, signal generators).
Board‑level troubleshooting and FPGA validation experience.
Full ASIC/FPGA lifecycle experience (architecture, design, simulation, verification, validation, integration & test).

Responsibilities

Capturing and translating system level performance, safety and reliability requirements into a detailed FPGA architecture.
Developing and verifying RTL using SystemVerilog/Verilog and Xilinx/AMD toolsets, creating synthesis, timing and power analysis reports.
Leading hardware in the loop (HIL) testing, board level debugging and integration with LWS turret closing subsystems.
Managing configuration control (GitLab or equivalent), maintaining version controlled design repositories and ensuring traceability of all artifacts.
Producing comprehensive design documentation, including specifications, test plans, verification reports and release packages compliant with aerospace standards.
Collaborating with cross functional teams—controls, software, mechanical, test, manufacturing and quality—to ensure seamless integration and compliance with program milestones.
Driving the design through to production release, coordinating with manufacturing, supply chain and test teams to validate manufacturability and reliability.
Conducting risk assessments, implementing mitigation strategies, and supporting failure analysis and corrective action activities.
Providing technical mentorship to junior engineers and promoting best practices in FPGA development, verification and configuration management.