ASIC/FPGA Design Engineer IV

Lockheed Martin•Littleton, CO

2d•Onsite

About The Position

Join Our Team as an ASIC & FPGA Design Engineer where you will support over 50 different programs and research and development (R&D) efforts, affecting technology across military space, civil space, commercial space, missiles, missile defense platforms, satellite surveillance platforms, deep space exploration, and manned flight missions. Location: This position does not support teleworking ; the selected candidate will be located near our Lockheed Martin Space facility in: Littleton CO You will work a flexible 9x80 schedule in the office full-time. What does this role look like? The Silicon Solutions team of Lockheed Martin Space is building the best ASIC/FPGA team in the world, and are seeking a highly talented and motivated ASIC & FPGA Design Engineer who has a passion for microchip design and space. Key activities you will accomplish in this role: Build and maintain strong technical relationships with multiple programs, serving as their trusted advisor and technical point of contact. Lead a high-performing team of up to 7 people, prioritizing and allocating daily tasks to ensure successful project execution across multiple concurrent initiatives. Develop and execute comprehensive project plans, delivering results within +/- 10% of schedule and budget while meeting agreed-upon quality metrics, and adapting Agile and Waterfall methodologies as needed to ensure successful outcomes. Proactively monitor and manage team member workloads, tracking progress against assigned tasks and labor capacity, while collaborating with project engineers and managers as needed to ensure clear communication regarding the teams execution. Foster a culture of technical excellence by providing guidance, mentorship, and expertise to team members on architecture, code, best practices, and command media, helping them to grow and develop their skills. Balance hands-on technical work with other leadership responsibilities, ensuring that technical tasks do not compromise ability to fulfill responsibilities such as team leadership, mentoring, and project oversight. Be responsible for the review and release of all work products to agreed quality standards. Collaborate with teams to identify, scope and plan new opportunities and support completed work. Perform advance chip architecture work for new programs and opportunities. Prepare regular status and loading reports as well as materials and data for operations reviews Assist manager in: o Reviewing and approving project plans o Technical proposal development, including scope capture and schedule development o Provide performance assessment input of individuals on your team o Program communication, issue de-escalation and risk mitigation o Determining team load capacity To be effective in this role, you will need: 5+ years professional experience. While no clearance is needed to start this position, you will need to obtain and maintain a Secret clearance , thus US Citizenship is required.

Requirements

5+ years professional experience.
While no clearance is needed to start this position, you will need to obtain and maintain a Secret clearance , thus US Citizenship is required.
Bachelor of Science or higher from an accredited college in Computer Engineering, Electrical Engineering or related discipline, or equivalent experience/combined education.
Experience in the design, debug and/or verification of any of the following: - FPGAs - Digital ASICs - Mixed-signal ASICs
HDL programming experience with VHDL, Verilog, and/or SystemVerilog.
Prior technical leadership experience preferred.
Linux development environment

Nice To Haves

Experience in leading or managing ASIC or FPGA projects.
Demonstrated self-starter and voracious learner
High EQ (Emotional Intelligence).
Space system design experience.
Understanding of system and hardware requirements related to space.
Microsoft Project or equivalent.
Microsoft Office.
Atlassian JIRA or equivalent.
Experience being a Control Accounts Manager (CAM) using Earned Value Management System (EVMS).
Customer-facing communication experience (product/services sales, marketing, field, etc.).
Ability to obtain a TS/SCI clearance.

Responsibilities

Build and maintain strong technical relationships with multiple programs, serving as their trusted advisor and technical point of contact.
Lead a high-performing team of up to 7 people, prioritizing and allocating daily tasks to ensure successful project execution across multiple concurrent initiatives.
Develop and execute comprehensive project plans, delivering results within +/- 10% of schedule and budget while meeting agreed-upon quality metrics, and adapting Agile and Waterfall methodologies as needed to ensure successful outcomes.
Proactively monitor and manage team member workloads, tracking progress against assigned tasks and labor capacity, while collaborating with project engineers and managers as needed to ensure clear communication regarding the teams execution.
Foster a culture of technical excellence by providing guidance, mentorship, and expertise to team members on architecture, code, best practices, and command media, helping them to grow and develop their skills.
Balance hands-on technical work with other leadership responsibilities, ensuring that technical tasks do not compromise ability to fulfill responsibilities such as team leadership, mentoring, and project oversight.
Be responsible for the review and release of all work products to agreed quality standards.
Collaborate with teams to identify, scope and plan new opportunities and support completed work.
Perform advance chip architecture work for new programs and opportunities.
Prepare regular status and loading reports as well as materials and data for operations reviews
Assist manager in: o Reviewing and approving project plans o Technical proposal development, including scope capture and schedule development o Provide performance assessment input of individuals on your team o Program communication, issue de-escalation and risk mitigation o Determining team load capacity