Our Hardware Engineering team is seeking an FPGA/ASIC Design Engineer to work with a multi-disciplined team to design, code, and verify FPGAs in our cutting-edge products in a fast-paced, process-oriented environment.
Deriving requirements from higher level specifications
Writing design documents
Designing and implementing register-transfer-level (RTL) code using Verilog
Designing with Vendor IPs and various industry standard interface protocols
Use of digital simulation tools to verify designs
Creation of physical design constraints for placement, timing closure and CDC
Implementation of designs into target technologies using synthesis and place and route tools
Perform timing analysis using static timing analysis tools
Perform lab debug of designs with laboratory equipment such as Logic Analyzers and oscilloscopes
Collaboration with other logic designers, board designers, software designers and ASIC designers
Communicating status to project leadership
BS/MS in Electrical Engineering
Minimum of 2+ years of industry experience
Knowledgeable in digital logic design
Experience in logic design writing RTL in Verilog HDL
Familiarity with a scripting language such as Python, TCL and Perl
Experience with physical design tools from FPGA vendors (Vivado or Quartus) or ASIC vendors
Ability to debug difficult problems using a variety of software and hardware tools (debugger, JTAG emulator, logic analyzer, and oscilloscope)
Highly motivated, team player, willing to pick up any piece of code, with a can-do attitude, and attracted to challenging opportunities
Excellent written and oral communication skills
Familiarity with high-speed serial protocols including PCIe and Ethernet
Familiarity with a digital simulation tool such as Synopsys, Cadence, or Mentor
High Speed digital circuit design
Familiarity with C/C++
Familiarity in the use of a source control tools
Familiarity working in a Linux based development environment