L3Harris Technologies-posted 9 months ago
Full-time • Entry Level
Camden, NJ
Computer and Electronic Product Manufacturing

L3Harris is dedicated to recruiting and developing high-performing talent who are passionate about what they do. Our employees are unified in a shared dedication to our customers' mission and quest for professional growth. L3Harris provides an inclusive, engaging environment designed to empower employees and promote work-life success. Fundamental to our culture is an unwavering focus on values, dedication to our communities, and commitment to excellence in everything we do. L3Harris Technologies is the Trusted Disruptor in the defense industry. With customers' mission-critical needs always in mind, our employees deliver end-to-end technology solutions connecting the space, air, land, sea and cyber domains in the interest of national security. Reporting to the Manager, Engineering (ASIC/FPGA), the Associate Member of Engineering Staff (AMES) will be part of the key ASIC/FPGA design team, responsible for the delivery of FPGA/ASICs for high-speed crypto applications. S/he will be part of design/verification team to implement high speed crypto architectures, on ASICs/Xilinx Zynq/MPSOC class FPGAs, with hands on design/debug with Ethernet, TCP/IP, PCIe, USB protocols. L3Harris has state-of-the-art EDA flows/methodologies including Synopsys DC/Primetime/Synplify, Xilinx/Intel/Microchip EDA with HLS, Mentor EDA Family suite : Questa, VIPs, UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, and Catapult (HLS). This role presents a great growth opportunity for a budding engineer, developing and delivering communication products for National Security. Upon joining the team, a mentor will be assigned to support assimilation and provide technical mentorship and guidance.

  • Responsible for deriving engineering specifications from system requirements and developing detailed architecture
  • Execute design (RTL AND/OR HLS (C++ to RTL)) and RTL quality (RDC, CDC, Formal, Lint)
  • Generate test plans
  • Perform module level verification, synthesis/STA, Lab debug, SW driven validation on Linux based SOC evaluation boards
  • Silicon/FPGA bring up, characterization and production ramp/support/collateral
  • BSEE, MSEE Preferred
  • 0-2 years Experience
  • Prior engineering internship/co-op experience, preferably in the Defense & Aerospace market
  • Exposure to VHDL, Vivado, Xilinx FPGAs
  • Strong logic/board debug, and analytical skills
  • Excellent written, verbal, and presentation skills
  • Active SECRET Clearance Preferred
  • Proficiency in C++ (OOP)
  • Proficiency with Xilinx MPSOC design with writing/debugging with SDKs, BSPs on bare metal/PetaLinux OS
  • Digital Signal Processing (DSP) background
  • Knowledge of protocols - TCP/IP, Ethernet, PCIe, NVMe, USB protocols
  • Experience with High level synthesis (Xilinx Vivado HLS, AND/OR Mentor Calypto)
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