ASIC Engineering Technical Leader

Cisco•San Jose, CA

6d•Onsite

About The Position

Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco’s silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon. Influence system architecture and key design decisions across complex SoC subsystems. Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure. Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets. Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation. Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon. Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges. Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team. Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.

Requirements

Bachelor’s degree in Electrical or Computer engineering and 8+ years of ASIC experience, or Master’s degree in Electrical Engineering or Computer Engineering and 6+ years of ASIC experience, or PhD in Electrical Engineering or Computer Engineering + 3 years of ASIC experience.
Experience in high-performance RTL design using Verilog/SystemVerilog.
Experience with timing closure, power optimization, and clock gating techniques.
Experience with ASIC development flows including simulation, synthesis, and static timing analysis.
Strong debug, problem-solving, and cross-team collaboration skills.

Nice To Haves

Understanding of data center networking and storage architectures, including RDMA and NVMe-over-TCP.
Experience with ARM-based SoC architectures and protocols such as AXI, CHI, APB, and AHB, and ARM IP including CMN, GIC, and SMMU.
Design experience with high-speed interfaces and controllers including PCIe, Ethernet MAC, DDR/LPDDR, and DMA engines.
Experience integrating third-party IP into complex SoC environments.
Proficiency in engineering automation and scripting (Python, Perl, TCL, shell).
Experience with emulation, prototyping, or formal verification tools.

Responsibilities

Drive the architecture and micro-architecture of high-performance ASIC subsystems for next-generation data center silicon.
Influence system architecture and key design decisions across complex SoC subsystems.
Work on some of the most challenging problems in high-performance silicon for hyperscale infrastructure.
Design and implement high-frequency, high-performance RTL in Verilog / System Verilog, meeting aggressive timing, power, and area targets.
Lead design specifications and technical reviews, ensuring architectural clarity and high-quality implementation.
Drive technical execution across architecture, design, verification, and physical implementation teams to deliver robust silicon.
Collaborate closely with verification and physical design teams to close functional coverage, timing, and integration challenges.
Mentor engineers and elevate engineering rigor, design quality, and technical execution across the team.
Lead debug and root-cause analysis across simulation, system bring-up, and post-silicon validation.

Benefits

U.S. employees are offered benefits, subject to Cisco’s plan eligibility rules, which include medical, dental and vision insurance, a 401(k) plan with a Cisco matching contribution, paid parental leave, short and long-term disability coverage, and basic life insurance.
Employees may be eligible to receive grants of Cisco restricted stock units, which vest following continued employment with Cisco for defined periods of time.
10 paid holidays per full calendar year, plus 1 floating holiday for non-exempt employees
1 paid day off for employee’s birthday, paid year-end holiday shutdown, and 4 paid days off for personal wellness determined by Cisco
Non-exempt employees receive 16 days of paid vacation time per full calendar year, accrued at rate of 4.92 hours per pay period for full-time employees
Exempt employees participate in Cisco’s flexible vacation time off program, which has no defined limit on how much vacation time eligible employees may use (subject to availability and some business limitations)
80 hours of sick time off provided on hire date and each January 1st thereafter, and up to 80 hours of unused sick time carried forward from one calendar year to the next
Additional paid time away may be requested to deal with critical or emergency issues for family members
Optional 10 paid days per full calendar year to volunteer
For non-sales roles, employees are also eligible to earn annual bonuses subject to Cisco’s policies.