ASIC Engineer Sr Staff

Hewlett Packard Enterprise-posted 3 months ago
$148,000 - $340,500/Yr
San Jose, CA
5,001-10,000 employees
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This role has been designed as ‘Hybrid’ with an expectation that you will work on average 2 days per week from an HPE office. Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.

  • Define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond.
  • Collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features.
  • Develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models.
  • Analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations.
  • Apply test constraints and perform STA analysis to ensure timing closure in test modes.
  • Support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF).
  • Conduct silicon failure analysis and contribute to system-level debug and yield improvement.
  • Automate DFT flows and analysis using scripting languages such as Perl and Tcl.
  • 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains.
  • Deep understanding of fault models: stuck-at, transition, path-delay.
  • Expertise in scan compression, ATPG, and MBIST architecture.
  • Experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair.
  • Proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler.
  • Simulation experience with Synopsys VCS and Cadence NC-Verilog.
  • Timing analysis using PrimeTime and Cadence Tempus.
  • Able to define test constraints and review STA reports to ensure timing closure in test modes.
  • Debugging with waveform tools such as Novas and SimVision.
  • Familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF.
  • Strong scripting skills in Perl and Tcl for automation and analysis.
  • Experience in silicon bring-up and system-level failure analysis for advanced process nodes (3nm and below).
  • Familiarity with high-speed networking protocols and system-level test strategies.
  • Exposure to yield analysis and production test optimization.
  • Health & Wellbeing: Comprehensive suite of benefits that supports physical, financial and emotional wellbeing.
  • Personal & Professional Development: Programs catered to helping you reach career goals.
  • Unconditional Inclusion: A work environment that celebrates individual uniqueness and varied backgrounds.
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