ASIC Engineer, Senior Staff, Physical Design Verification
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About The Position
The ASIC Physical Verification Engineer will develop and support block and full chip automated physical verification flows and scripts. This role involves building Fullchip netlist & oasis database, executing metal and base-layer fill, and integrating various components. The engineer will perform block and full-chip physical verification, debug issues, and collaborate with the physical design team to resolve design issues. Additionally, the engineer will work with the PD team to address all DRC/LVS/ESD/ERC/ANT/DFM/latchup violations, rule deck issues, and sign off PV for tapeouts. Close collaboration with semiconductor foundries and partners on the installation and maintenance of process design kits (PDKs) for ASIC physical design teams is also required. The engineer should understand and assist the PD team on pad ring, bump, RDL design, and work with the package and floorplan teams.
