ASIC Engineer, Power

Meta-posted about 2 months ago

Full-time

Sunnyvale, CA

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Develop power vectors for estimation and optimization.
Low-power design of ASIC modules.
Run industry standard EDA power simulation tools on customized ASIC designs.
Power estimation and optimization strategies for all layers of abstraction in silicon design, from architecture to physical design.
Develop power vectors for estimation and optimization.
Low-power design of ASIC modules.
Run industry standard EDA power simulation tools on customized ASIC designs.
Power estimation and optimization strategies for all layers of abstraction in silicon design, from architecture to physical design.
Develop internal tooling for performance and power improvement for ASICs.
Reduce arithmetic unit and data-path power while reducing area and increasing performance in new generation hardware accelerators.
Formulate circuit and data-path abstractions using mathematical models.

Bachelor's degree (or foreign degree equivalent) in Computer Science, Engineering, Mathematics, Physics, Applied Sciences, or a related field and 2 years of experience in the job offered or in a computer-related occupation
Experience must include 2 years of experience in the following:
C, C++, Java, TCL, and Python Programming
Writing RTL code using Verilog/SystemVerilog or VHDL
Mathematical modeling of ASIC physical feature phenomenon
Frontend power analysis and optimization tools (Prime Power RTL / RTL Architect) with experience in RTL design or validation
Backend power estimation tools and flows including development and analysis (Prime Power / Power Replay) to perform power estimation, analysis and optimization at various stages of the design
UPF generation, verification (VC Low Power), and signoff for complex SoC projects
Understanding of Computer Architecture including various design tradeoffs and how they affect power and
Experience generating Thermal and Power maps to understand hotspots and power density in an ASIC using mathematical modeling software (MATLAB)

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