ASIC Engineer, Implementation

Meta-posted 3 months ago
$171,206 - $192,170/Yr
Full-time • Entry Level
Sunnyvale, CA
Computing Infrastructure Providers, Data Processing, Web Hosting, and Related Services
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Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps and services like Messenger, Instagram, and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology.

  • Run logic/physical synthesis using advanced optimization techniques and generate optimized gate level netlist for Timing, Area, and Power.
  • Debug timing/area/congestion issues and resolve with RTL & physical designers.
  • Perform power estimation at RTL & gate level and identify power reduction opportunities.
  • Run formal verification checks between RTL & gate level netlist and debug aborts, inconclusive and logic equivalency failures.
  • Perform RTL lint and work with designers to create waivers.
  • Perform RTL DFT analysis and improve DFT coverage for stuck-at faults.
  • Perform flat and hierarchical clock domain crossing, work with designers to analyze complex clock domain crossings and sign off CDC.
  • Perform flat and hierarchical reset domain crossing checks.
  • Understand reset-architecture and work with design & FW teams to develop reset groups and corresponding reset sequence for RDC.
  • Develop timing constraints for RTL-synthesis and PrimeTime-STA for blocks and top-level including SOC.
  • Analyze inter-block timing and create IO budgets for various partition blocks.
  • Develop automation scripts and methodology for FE-tools.
  • Support design engineers, DV engineers, and emulation engineers with handoff tasks.
  • Give timing/congestion feedback.
  • Requires a Master's degree (or foreign degree equivalent) in Computer Science, Computer Engineering, Electrical Engineering, or a related field and one year of work experience in the job offered or in a computer-related occupation.
  • Requires one year of experience in the following: Logic synthesis and design optimization for Power, Performance, and Area.
  • Floor Planning and Placement.
  • Physical Design Execution for Clock Tree Synthesis and Routing optimization.
  • Static timing analysis and verification at different PVT corner.
  • Timing ECO using PrimeTime.
  • Working with cross-functional teams to support and debug timing, area, and power issues.
  • Flow Automation with TCL, Python, or Perl.
  • Bonus
  • Equity
  • Health benefits
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