ASIC Design Verification Engineer

Advanced Micro Devices, Inc • Boxborough, MA

1d • Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Plan, create and execute the tests, testbenches, tools and environment necessary to integrate IP blocks into SOC projects for the Strategic Silicon Solutions (S3) team. You will help create custom SOC solutions for AMD S3 customers like the PlayStation 5 (PS5) from Sony Computer Entertainment Inc. (SCEI), the Xbox Series X from Microsoft, and the Steam Deck from Valve. THE PERSON: You have a passion for modern, complex processor architecture, digital design, and verification in general. You are willing to dig in and understand legacy tools and processes and improve them. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

Requirements

• Proficient in SOC & IP level ASIC verification.
• Proficient in debugging RTL code using simulation tools.
• Proficient in using UVM testbenches and working in Linux and Windows environments.
• Experienced with Verilog, System Verilog, C, and C++.
• Strong background in C++, preferably on Linux with exposure to Windows platform.
• Developing UVM based verification frameworks and testbenches, processes and flows.
• Automating workflows in a distributed compute environment.
• Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process.
• Good understanding and hands-on experience in the UVM concepts and SystemVerilog language.
• Scripting language experience: Perl, Ruby, Makefile, shell preferred.
• Bachelors or Masters degree in Computer Engineering/Electrical Engineering.

Nice To Haves

• Exposure to leadership or mentorship is an asset.

Responsibilities

• Collaborate with architects, hardware engineers, and others to understand the new features to be verified.
• Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases.
• Estimate the time required to write the new feature tests and any required changes to the test environment.
• Build the directed and random verification tests.
• Debug test failures to determine the root cause; work with RTL engineers to resolve design defects and correct any test issues.
• Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees