ASIC Design Verification Engineer (Security Group)

Qualcomm • Santa Clara, CA

71d • $140,000 - $210,000 • Remote

About The Position

As a leading technology innovator, Qualcomm pushes the boundaries to enable next generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Design Verification Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, validate digital/analog designs and develop a comprehensive validation/verification testbench environment for projects that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions that meet performance, security, technology, and feature requirements. As a Design Verification Engineer, you will work with Chip Architects to validate the concepts of core and sub-system level micro-architectures. You will work on a selected part of the subsystem Design Verification to ensure that it functions to the standards of being launch ready for the end Product.

Requirements

• Minimum Experience Level should be 2+ years in SOC-level or core-level verification with good understanding of debugging either ARM-based or RISC-V based processors.
• Good understanding of APB/AHB/AXI protocols.
• Solid understanding of SV/UVM concepts.
• Prior experience in any cryptographic algorithm is preferred.
• Must have basic understanding of UNIX commands and Python/Perl scripting.
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Nice To Haves

• Deep knowledge of APB/AXI/SPI protocols, handshake mechanisms, cross-clock domains and clock gating.
• Solid understanding of memory organization, fault-tolerant design, parity schemes, error detection and error correction schemes.
• Advanced techniques such as: Formal, Assertions, and Silicon bring-up, is helpful.
• In-depth knowledge of Micro-processor functions, Network-on-Chip Architectures, and Micro-architectures.
• Experience in writing Testplans, portable Testbenches, Transactors, and Assembly code.
• Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Mixed signal Verification.
• Ability to develop and work independently on a Block/Unit of the design.

Responsibilities

• Work with subsystem and SOC Architects to understand the concepts and high-level system requirements.
• Develop detailed Test and Coverage plans based on the Architecture and Micro-architecture.
• Develop Verification Methodology, ensuring scalability and portability across environments.
• Develop Verification environment, including all the respective components such as Stimulus, Checkers, Monitors Assertions, and Coverpoints.
• Develop Verification Plans and Testbenches for your functional domain.
• Execute Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures.
• Track and report DV progress using a variety of metrics, including Bugs and Coverage.

Benefits

• $140,000.00 - $210,000.00 salary range.
• Competitive annual discretionary bonus program.
• Opportunity for annual RSU grants.
• Highly competitive benefits package designed to support your success at work, at home, and at play.

What This Job Offers

• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees