About The Position

Our work at NVIDIA is dedicated towards a computing model focused on visual and AI computing. For two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics, with our invention of the GPU. The GPU has also shown to be spectacularly effective at solving some of the most complex problems in computer science. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots and self-driving cars that can perceive and understand the world. We are looking to grow our company and teams with the smartest people in the world and there has never been a more exciting time to join our team! As a member of the NVLink ASIC Design team, located in Westford, MA, you will work with a worldwide team of architects and engineers dedicated to raising the bar for high speed chip to chip communication. We are a fast-paced, energetic team dedicated to meeting the customer requirements emerging from the datacenter marketplace.

Requirements

  • Bachelors Degree in EE, CS or CE (or equivalent experience)
  • Strong working knowledge of Verilog or System Verilog
  • Project and/or design experience with high speed (>1GHz) design.
  • Project and/or design experience with low power design methodologies.
  • Strong collaboration and communication skills

Nice To Haves

  • Internships and/or project experience with Verilog/system verilog.
  • Background with low power design methodologies
  • Experience with high speed design methodologies

Responsibilities

  • Engaging in and support the design and development of NVIDIA’s next generation NVLink protocol.
  • Participating in microarchitecture development and document specifications.
  • Implementing in RTL and debug working with the verification team to ensure that the design is functional and performant.
  • Applying logic design skills to optimize and meet performance and power goals.
  • Delivering a synthesis/timing clean design while working with the physical design team to ensure a routable and physically implementable design.
  • Supporting hardware engineering activities including chip floor plan, power/clock distribution, timing closure, power and noise analysis, and back-end verification.
  • Developing flows and tools as necessary in support of design activities.
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