ASIC Design Engineer, Senior

Tokyo Electron
2dOnsite

About The Position

Let’s search for your next career at TEL. Use the form below to search our current opportunities and then apply. Please consider joining our Talent Community so that we may continue to engage with you. We make innovation possible. At TEL, we’re committed to advancing future technologies and success starts with a community of talented individuals. Our global workforce of over 20,000 employees is embracing the challenge of a rapidly evolving tech landscape. Your growth fuels our progress. Our 360-degree learning approach ensures there’s something for every style from interactive classes and on the job training to formal programs led by certified technical experts and organizational development professionals. You’ll continue building your skills and nurturing your curiosity. To support your journey, TEL offers educational reimbursement to help you reach your learning goals.

Requirements

  • Strong understanding of the Python language, EDA flow scripting, and custom schematic/layout tools
  • Bachelor’s degree (or equivalent) in Electrical Engineering, Computer Engineering, or Computer Science required
  • B.S. with 5+ years or M.S. with 2+ years of relevant industry experience preferred
  • Excellent verbal and written communication skills

Nice To Haves

  • Experience with scientific Python libraries such as numpy, pandas, and matplotlib is desired
  • Hands-on experience or familiarity with RTL design and verification methodologies
  • Knowledge of analog circuit design principles and layout considerations is a plus

Responsibilities

  • Support the design and implementation of custom VLSI test chips
  • Develop Python-based scripts to automate schematic and layout tasks for custom ASIC circuits
  • Complete top-level chip layout and physical verification
  • Perform pre-silicon verification simulations, including RTL verification
  • Collaborate closely with EDA tool providers and test engineering teams
  • Assist in the design and verification of both RTL and analog circuit blocks to ensure seamless integration within ASIC designs

Benefits

  • TEL offers educational reimbursement to help you reach your learning goals.
© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service