ASIC Design Engineer Intern

Ambarella-posted 3 months ago

Entry Level

Smyrna, GA

501-1,000 employees

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Our solutions make cameras smarter by extracting valuable data from high-resolution video streams. Combining technical expertise and a commitment to quality, Ambarella has established itself as the industry standard for excellence in video performance by offering pristine imagery, efficient compression, and low-power operation. For our next phase of growth, we are looking for talented team members to help us deliver our advanced computer vision algorithms to tomorrow’s intelligent video products. Our target applications include autonomous vehicles, intelligent video surveillance, self-flying drones, smart wearable cameras, 360-degree immersive video, and more.

Designing and implementing video compression logic, image processing logic, vector processing and neural network accelerator logics, and processor cores, in Verilog and System Verilog.
Logic design, implementation, and verification using Verilog, System Verilog, and any required programming and scripting languages.
Synthesize and optimize RTL for timing, area and power.
Developing unit level and cluster level test-benches, BFMs, random test generators, functional coverage monitors, using System Verilog, UVM, C++, and Perl scripts.
Developing test plan, random and directed test cases, performing logic verification, and functional coverage analysis.
Developing front-end methodologies and tool flows.
Participating in chip bring-up and testing.

Master’s degree in Electrical/Electronics/Computer Engineering with 0-5 years of experience.
Good understanding of computer architecture, logic design and VLSI design.
Knowledge of System Verilog, Verilog, and Perl.
Knowledge of design verification, and functional coverage.
Ability to program scripting languages and the ability to write assembly language programs.
Strong communication skills and a good team player.
Knowledge of logic synthesis and timing closure.

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