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The position involves designing and implementing various logic systems including video compression logic, image processing logic, vector processing, and neural network accelerator logics, as well as processor cores using Verilog and System Verilog. The role requires a strong focus on logic design, implementation, and verification, utilizing Verilog, System Verilog, and necessary programming and scripting languages. Additionally, the candidate will be responsible for synthesizing and optimizing RTL for timing, area, and power efficiency. The position also includes developing unit level and cluster level test-benches, bus functional models (BFMs), random test generators, and functional coverage monitors using System Verilog, UVM, C++, and Perl scripts. The candidate will need to create test plans, develop random and directed test cases, and perform logic verification and functional coverage analysis. Furthermore, the role involves developing front-end methodologies and tool flows, as well as participating in chip bring-up and testing.
