ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team

Amazon.com-posted 2 months ago
$129,800 - $212,800/Yr
Austin, TX
5,001-10,000 employees
General Merchandise Retailers
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AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS, including support for customers who require specialized security solutions for their cloud services. Annapurna Labs (our organization within AWS UC) designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world.

  • Integrate multiple subsystems into top level SOC, ensure correct clock/reset/functional/DFT signal routing.
  • Implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications.
  • Analyze design, microarchitecture or architecture to make trade-offs based on features, power, performance or area requirements.
  • Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/timing clean design with constraints.
  • Perform lint and clock domain crossing quality checks on the design.
  • Work with architects, other designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks.
  • B.S. in Electrical Engineering or related technical field.
  • 3+ years in RTL design for SOC.
  • 3+ years of VLSI engineering.
  • 3+ years with code quality tools including: Spyglass, LINT, or CDC.
  • Master's degree in electrical engineering, computer engineering, or equivalent.
  • Experience with Microarchitecture, SystemVerilog RTL, Assertions, SDC constraints.
  • Experience with automation and scripting languages such as Python.
  • Familiarity with data path design, interconnects, AXI protocol.
  • Good analytical, problem solving, and communication skills.
  • Medical, financial, and/or other benefits.
  • Equity, sign-on payments, and other forms of compensation may be provided as part of a total compensation package.
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