ASIC Design Engineer - Cache Controller

Apple • Santa Clara, CA

77d

About The Position

Apple is building the world’s fastest highly parallel mobile processing systems. Our high-bandwidth multi-client memory subsystems are blazing new territory with every generation. As we increase levels of parallelism, bandwidth and capacity, we are presented with design challenges exacerbated by clients with varying but simultaneous needs such as real-time, low latency, and high-bandwidth. In this role, you will work on crafting special purpose cache and controller which is part and parcel of the SOC memory hierarchy.

Requirements

• In-depth knowledge of memory subsystem
• Academic experience with RTL/micro-architecture development
• Good understanding of PPA (performance/power/area) tradeoffs
• B.S. in a relevant field + 0 years of industry experience

Nice To Haves

• Cache design background including good understanding of different memory organizations and tradeoffs
• Experience with multi-processor cache coherence protocols
• Knowledge of high-performance coherent memory systems or interconnect architectures
• Knowledge of high-performance DRAM controller
• M.S in a relevant field

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Education Level: Bachelor's degree
• Number of Employees: 5,001-10,000 employees