ASIC Clocks Design Engineer - New College Grad 2025

Nvidia • Santa Clara, CA

88d • $108,000 - $184,000

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. Make the choice to join us today. The clocks group is looking for an outstanding ASIC engineer to join the team. The Team is responsible for crafting all aspects of GPU and CPU clocking. The team collaborates with the front design team to understand the clocking requirements for the chip. The clocks team interacts with the floor-planning and back end team to help craft the physical floorplan of the chip. The team explains the programming model to the SW team to come up with an efficient clock programming sequence. The team works with the silicon solution team to triage silicon or programming bugs in the lab.

Requirements

• BS or higher in Electrical Engineering (or equivalent experience).
• Understanding of logic optimization techniques and PPA trade-offs.
• Excellent interpersonal skills and ability to collaborate with multiple teams.
• Experience in RTL design (Verilog), verification and logic synthesis.
• Strong coding skills in python or other industry-standard scripting languages.

Nice To Haves

• Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects.
• Implementing on-chip clocking networks.

Responsibilities

• Architect the clock domain to satisfy functional, physical and testing design requirements.
• Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.
• Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
• Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.
• Deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
• Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.

Benefits

• Equity and benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level
• Industry: Computer and Electronic Product Manufacturing
• Education Level: Bachelor's degree