Synopsys-posted 8 months ago
$134,000 - $201,000/Yr
Full-time • Senior
Onsite • Morrisville, NC
Publishing Industries

You are a passionate and innovative engineer with a deep understanding of IC design flows, particularly in design layout & reliability verification. Your expertise in EDA software for physical verification, ESD analysis, circuit simulation, parasitic extraction and related fields makes you an asset. You thrive in environments where you can collaborate with customers and foundry partners, driving the next generation of reliability verification solutions. Your ability to translate complex customer requirements into actionable solutions sets you apart. You are a self-starter with excellent communication skills, capable of working in cross-functional teams and managing multiple projects simultaneously.

  • Create product specifications and roadmaps for IC Validator's PERC reliability verification platform.
  • Collaborate with key customers and foundry partners to define next-generation reliability verification EDA solutions.
  • Support customer product evaluations by introducing ICV PERC to engineering stakeholders, setting up custom and foundry-defined reliability flows.
  • Guide internal foundry-facing teams to create best-in-class and on-time ICV PERC PDKs at leading foundries.
  • Work with cross-functional R&D engineers to drive product priorities and software development, considering overall business landscape and customer needs.
  • Serve as the point-of-contact for Field Engineering teams regarding advanced product needs related to PERC and ESD verification.
  • Evangelize existing and upcoming functionality of ICV PERC software to build trust with field engineers and customers.
  • Understanding of IC design flow with emphasis on design layout verification, ESD analysis, circuit simulation, parasitic extraction, and electro migration checks.
  • Understanding of ESD models & static/dynamic ESD verification tools and methodologies.
  • Experience with EDA tools such as Ansys PathFinder, Siemens Calibre PERC, Cadence Pegasus, Synopsys StarRC.
  • Experience in chip tapeouts with an emphasis on ESD reliability sign-off.
  • Experience in PDK management and foundry rule deck development for physical and reliability verification.
  • Proficiency in at least one object-oriented programming language and code maintenance system (Perforce/GitHub). Prior experience in Python is preferred.
  • Strong understanding of parasitic extraction and circuit simulation in EDA.
  • Comprehensive health, wellness, and financial benefits.
  • Annual bonus eligibility.
  • Equity and other discretionary bonuses.
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