Analog/Mixed Signal Verilog Modeling Design Engineer

Broadcom • San Jose, CA

11h

About The Position

Responsible for developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language. Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.

Requirements

• Understand Verilog-AMS modeling language
• Good knowledge of SystemVerilog UDT/UDR nettype (using Cadence wreal or EEnet package)
• Familiar with analog circuits such as LDOs, TIAs, analog muxing, SARADC sample-and-hold (S/H), comparators, DAC voltage converter, buffering and amplification, etc.
• Understand good coding of RTL of digital design (eg clock divider, decoder, FSM, etc) and testbench creation.
• Fully familiar with how to run SV .vs. schematic verification for a given leaf SV model.
• Familiar with Cadence linting & simulation tools (ncsim, xrun, vcs) and analog schematic editor.
• Hands-on skills in scripting languages (TCL/Perl/Python)
• Bachelor's and 8+ years of related experience

Nice To Haves

• Experience with using AI tools such as Cursor, chipAgents to generate analog SV models and testbench based on a given design spec.

Responsibilities

• Developing Digital-Mixed Signal (DMS) models of analog IPs such as touch controller AFEs, wireless power charging, health sensing AFE and satellite AFEs using SystemVerilog language.
• Interface with analog design team and chip DV team to develop and support analog/mixed signal models for chip verification.

Benefits

• Medical, dental and vision plans
• 401(K) participation including company matching
• Employee Stock Purchase Program (ESPP)
• Employee Assistance Program (EAP)
• company paid holidays
• paid sick leave and vacation time

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees