In this role you will contribute to the design, integration and validation of high-performance analog and mixed-signal circuits for SerDes PHY applications. This encompasses the design and optimization of critical building blocks such as receivers, transmitters, bias generators, high-speed clock generation and distribution networks targeting best-in-class power, performance, and area metrics. A key part of your design responsibilities will include the development of analog DFT circuits and techniques essential for comprehensive PHY validation. You will develop test plans, review and analyze data to guarantee a robust IP design. You will drive and work closely with production test (e.g. ATE, system validation) teams and debug complex design and system bring-up issues. You will collaborate closely with cross-functional teams including architecture, RTL design, verification, signal integrity, packaging, board design, DFT and ESD to ensure seamless PHY integration, feature verification and power delivery. This position offers substantial technical leadership opportunities and a direct impact on the development of next-generation high-speed connectivity solutions. You will thrive in a collaborative environment, engaging regularly with peers and management, fostering innovation, technical growth and career development.