Analog Mixed Signal IC Designer

Apple-posted 2 months ago
Waltham, MA
5,001-10,000 employees
Computer and Electronic Product Manufacturing
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We are seeking motivated Analog Mixed-Signal designers to join our high-speed SerDes team. Our team specializes in building next generation high-performance wireline transceivers delivering intellectual-property (IP) for Apple's world-leading system-on-chip (SOC)! In this role, you will actively work with cross-functional Analog Mixed-Signal design teams to create state-of-the-art IPs key to Apple's products. You will be challenged to make the best-in-class designs to surprise and delight Apple customers. With transforming the user experience in focus, you will get an opportunity to work on designs which makes the best systems. This enables you to learn to end-to-end system while exceeding the highest expectations of quality, innovation and efficiency.

  • Develop high-performance and high-speed AMS circuits used in SerDes PHY.
  • Evaluate different circuit topologies for specific product requirements (e.g., Rx, CDR, Tx, bias generator, high-speed clock generation and low-jitter distribution, phase interpolator, DLL, VCO, LDO).
  • Lead discussions with multi-functional teams (e.g., architecture, SIPI, packaging, board design, DFT, ESD) to create and drive block-level specifications.
  • Implement mixed-signal designs and behavioral modeling.
  • Work closely with SOC teams to deliver IP views and ensure they meet quality standards.
  • Communicate progress, discuss new ideas, and drive new implementations/concepts.
  • Demonstrated proficiency in high-speed analog/mixed-signal architecture and circuit design.
  • Strong understanding of frequency synthesizers, ADCs, DACs, RO/LC oscillators, regulators, on-chip sensors, compensation techniques, droop detection and recovery, and digitally-assisted analog techniques.
  • Deep understanding of clocking fundamentals, including phase noise, jitter analysis, budgeting, and feedback loop dynamics.
  • Skilled in designing/debugging RTL and developing System Verilog models.
  • Exceptional focus on understanding problems and their systemic impacts.
  • Experience with timing closure concepts and related industry tools (e.g., Nanotime, Primetime).
  • Knowledge of IP delivery and quality checks.
  • Familiarity with common high-speed SerDes protocols (e.g., PCIe, USB, DP, MPHY).
  • Skills in scripting and automation to improve efficiency.
  • Outstanding teamwork capabilities paired with strong productivity and scripting skills.
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