Analog Mixed-Signal Design Co-Op

NXP Semiconductors•San Jose, CA

21d•$64,480 - $107,500

About The Position

We are looking for an early‑career engineer to support AMS (Analog‑Mixed‑Signal) + Digital Integration activities for next‑generation semiconductor designs. This position provides hands‑on exposure to: Mixed‑signal IP integration Basic RTL coding and digital build flows AMS simulation environments Lab validation and measurements Cross‑functional collaboration (analog design, digital design, verification, CAD) You will work closely with experienced engineers who will mentor you in full‑chip integration, mixed‑signal verification, and silicon bring‑up—ideal preparation for an MSEE program or an early engineering career. Key Responsibilities Mixed‑Signal Integration (Entry-Level Scope) Assist in integrating analog and digital blocks into top‑level AMS environments. Prepare schematic and netlist views used for AMS simulations. Run automated connectivity and interface checks under supervision. Support mixed‑signal view generation (symbol, Verilog, Verilog‑AMS, wreal). RTL Coding & Digital Support Write and modify simple RTL modules (wrappers, muxes, registers, glue logic). Assist with integration into digital‑on‑top flows: Linting Elaboration Basic synthesis checkpoints Create small testbench utilities to validate RTL functionality. AMS Simulation & Verification Tasks Run AMS simulations (Spectre/Xcelium/AMS Designer) for block‑ and top‑level tests. Collect waveforms, create summary plots, and help analyze failures. Update or create simple AMS testbenches and configuration files. Lab Validation & Silicon Bring‑Up (Hands-on) Support bench measurements for AMS blocks and subsystems: Oscilloscope measurements Power‑up sequences Data capture using automation scripts Reproduce issues seen in silicon or lab setups. Follow proper lab/equipment handling and safety procedures. Tool Flow & Documentation Assist in model packaging, scripting, and build logistics. Update internal documentation, integration guides, and test logs. Participate in team meetings and cross‑discipline design reviews.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, or closely related field.
Solid academic grounding in: Analog circuits Digital logic design SPICE simulation HDL coding (Verilog preferred)
Hands‑on experience through coursework or projects with: Oscilloscopes, logic analyzers, power supplies SPICE / Cadence / Mentor simulation environments Simple RTL coding and testbenches
Comfort with Linux, scripting basics (Python, Bash, TCL).
Strong communicator, organized, and eager to learn.

Nice To Haves

Completed senior‑level coursework or projects in: Data converters (ADC/DAC) PLLs or clocking circuits Mixed‑signal IC design
Familiarity with Verilog‑AMS, SystemVerilog, or wreal modeling.
Prior lab/Co‑op experience in semiconductor or embedded domains.
Exposure to Git, revision control, and automation scripts.

Responsibilities

Assist in integrating analog and digital blocks into top‑level AMS environments.
Prepare schematic and netlist views used for AMS simulations.
Run automated connectivity and interface checks under supervision.
Support mixed‑signal view generation (symbol, Verilog, Verilog‑AMS, wreal).
Write and modify simple RTL modules (wrappers, muxes, registers, glue logic).
Assist with integration into digital‑on‑top flows: Linting Elaboration Basic synthesis checkpoints
Create small testbench utilities to validate RTL functionality.
Run AMS simulations (Spectre/Xcelium/AMS Designer) for block‑ and top‑level tests.
Collect waveforms, create summary plots, and help analyze failures.
Update or create simple AMS testbenches and configuration files.
Support bench measurements for AMS blocks and subsystems: Oscilloscope measurements Power‑up sequences Data capture using automation scripts
Reproduce issues seen in silicon or lab setups.
Follow proper lab/equipment handling and safety procedures.
Assist in model packaging, scripting, and build logistics.
Update internal documentation, integration guides, and test logs.
Participate in team meetings and cross‑discipline design reviews.