Analog/Mixed Signal ASIC Design Engineer

Qualcomm • San Diego, CA

4d

About The Position

QCT Mixed-Signal IP (MSIP) design team is looking for talented analog integrated circuit designers at various levels to help with designing high-performance and low-power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) in advanced silicon process technologies. These are widely used in Qualcomm’s SOCs and RF transceiver products targeted for 5G, AI/ML, compute, and automotive applications. MSIP design team consists of architects, analog/mixed signal and digital designers, protocol and signal processing experts, and algorithm designers, and we are looking for new talents in the area of analog circuit design for our SOCs.

Requirements

• Master's degree in Electrical Engineering or related field.
• Demostrated interrest in analog circuit design by course selections and/or work experience.
• Experience working with ASIC design tools such as Cadence Virtuoso.
• Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 2+ years of ASIC design, verification, or related work experience.
• OR
• Master's degree in Electrical Engineering or related field and 2+ years of ASIC design, verification, or related work experience.
• OR
• PhD in Electrical Engineering or related field.
• 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).

Nice To Haves

• Several years of industry experience in the area of analog integrated circuit/system design.
• Experience as an analog designer of mixed-signal IPs, such as SerDes, DDR, PLL, DAC, ADC, sensors
• Familiar with Matlab and Python and good understanding of architecture, system and integration aspects for mixed-signal
• Good understanding of design for yield and production challenges
• Good understanding of Signals and Systems, Sampled Domain signal processing a plus

Responsibilities

• Work in our MSIP analog design team to develop various mixed-signal IP above including architecture definition, and analog/digital design partitioning and schematic design.
• Schematic capture and circuit simulations in the Cadence Virtuoso tool suite.
• Work with cross functional teams (i.e. layout and digital teams) on design implementation, verification and IP delivery to SOC customers
• Work with product test teams for post-silicon verification, bringup, debug, and production support

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees