Analog Layout Senior Staff Engineer

Marvell•Santa Clara, CA

35d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. As an Analog Layout Senior Staff Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a small analog team making a big impact on this organization. Additionally, Marvell has the perfect size and scale for you to learn several aspects of engineering that will be new to you, but also have the time and freedom to dive deep into the details of your specialization on most projects. Working with global teams across Argentina, Singapore, the U.S., and Europe, you will run simulations and verifications using Cadence Virtuoso, collaborating closely with the designer to refine and debug iteratively until the design meets specifications. Project durations vary from a few months to a year and a half with flexibility to switch based on changing priorities is appreciated. Regular meetings with your paired designer ensure collaborative information sharing, integral to Marvell's commitment to partnership and teamwork. As a key contributor, you play a crucial role in the project lifecycle, participating in routine meetings as a technical mentor, layout team, and the broader project team. These interactions include updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies. The dynamic nature of our work ensures continuous learning and knowledge-sharing among colleagues.

Requirements

Have fundamental understanding of electrical concepts, likely acquired through a degree in Electrical Engineering (graduate or undergraduate).
Know how to use CAD tools to do the implementation layers, microelectronic layers in design that go beyond the schematics.
Track record of delivering high-speed or precision analog circuits, preferably in multiple process nodes
Have ownership through the full development cycle: floorplan, layout, verification, delivery, and support
Assume more responsibility and ownership of tasks, from cells to functional blocks, to higher-level macros, to full interfaces or chips
Have excellent communication skills to give status updates to your team, present to global teams in different time zones, and to share information with many different levels of personnel at Marvell

Responsibilities

Run simulations and verifications using Cadence Virtuoso
Collaborate closely with the designer to refine and debug iteratively until the design meets specifications
Participate in routine meetings as a technical mentor, layout team, and the broader project team
Provide updates on progress and may involve presenting specific issues or solutions encountered during the development of cutting-edge technologies