Analog IC Design, Principal Engineer

Marvell Technology • Santa Clara, CA

98d • $165,630 - $248,100

About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The CE AMS PHY group supports analog mixed-signal product development for High-Speed Ethernet PHY businesses in Marvell. You will be working with multi-functional teams to deliver high-speed Ethernet products. You will define specifications based on link budget, behavioral modeling, and transistor-level feasibility. You will also drive schematic design and collaborate on mask design for implementation. And finally, with the team, you will drive designs into volume production and delight customers.

Requirements

• Master’s degree and/or PhD in Electrical Engineering.
• 5+ years of experience in analog mixed-signal design with experience in high-speed transceivers.
• Solid understanding and experience of designing analog mixed-signal circuit blocks including PLL, phase interpolator, low jitter clock distribution, Bandgap, biasing circuits, LDO regulators, amplifiers, comparators, high-speed DACs and ADCs, Filters.
• In-depth knowledge of analog mixed-signal concepts like mismatch mitigation, linearity, stability, low-power and low-noise techniques.
• Experience with high-speed digital circuits (e.g., serializer, deserializer, counters, dividers, etc.).
• Hands-on experience with AMS IC development from definition to high-volume production including layout supervision, bench evaluation, correlation, and characterization.
• Experience in lab testing of high-speed transceivers.

Responsibilities

• Define specifications based on link budget, behavioral modeling, and transistor-level feasibility.
• Drive schematic design and collaborate on mask design for implementation.
• Work with multi-functional teams to deliver high-speed Ethernet products.
• Drive designs into volume production.

Benefits

• Flexible time off
• 401k
• Year-end shutdown
• Floating holidays
• Paid time off to volunteer

What This Job Offers

• Career Level: Senior
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees