Analog IC Design Engineer, Principal Engineer

Marvell • Santa Clara, CA

28d

About The Position

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Central Engineering AMS-IP team provides leading-edge SerDes and Chiplet IO PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. Seeking a Principal Analog IC Designer to be part of a Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/PLL products. Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. In this role, successful candidate will lead a team of analog design engineers, interface with layout, verification, and application teams and manage delivery of analog IP to successfully bring designs from concept to production.

Requirements

• Master's degree and/or PhD Preferred in Electrical Engineering or related fields with 10+ years of experience.
• PLL, Data Converters, Oscillators and high-speed SerDes design including Receiver and Transmitter design.
• Experience with analog design and verification tools (Virtuoso, Spectre, ADE and post layout extraction tools) is a must
• Knowledge of the fundamentals on signal integrity improvement, noise reduction and Multi-GHz low-jitter clock generation & distribution.
• Good understanding of analog layouts in FinFet and its effect on high-speed designs
• Experienced in system level pre-tape out analog validation
• Experienced in lab chip bring-up and debugging efforts
• Strong communication skills

Nice To Haves

• Experience with design D2D interface such as UCIe a plus
• Experience with 112G+ SerDes speed, especially short reach and low power designs
• Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication, DDR5/LPDDR5; GDDR6/LPDDR6 a plus

Responsibilities

• architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets
• performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc.
• lead a team of analog design engineers
• interface with layout, verification, and application teams
• manage delivery of analog IP to successfully bring designs from concept to production.

Benefits

• flexible time off
• 401k
• year-end shutdown
• floating holidays
• paid time off to volunteer

What This Job Offers

• Job Type: Full-time
• Career Level: Principal
• Industry: Computer and Electronic Product Manufacturing
• Number of Employees: 5,001-10,000 employees