Analog IC Design Engineer, Principal Engineer

Marvell Technology • Santa Clara, CA

64d • $165,630 - $248,100

About The Position

Seeking a Principal Analog IC Designer to be part of Marvell's central engineering team designing highly sophisticated CMOS transceiver/SERDES/PLL products. Responsibilities would span architectural investigations and implementation for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, CDRs etc. to meet key performance targets and performing design verification using industry standard tools such as SPICE, Spectre, MATLAB etc. In this role, successful candidate will lead a team of analog design engineers, interface with layout, verification, and application teams and manage delivery of analog IP to successfully bring designs from concept to production.

Requirements

• Master’s degree and/or PhD in Electrical Engineering or related fields.
• 10+ years of experience in analog IC design.
• Experience in PLL, Data Converters, Oscillators, and high-speed SerDes design.
• Experience with design D2D interface such as UCIe.
• Experience with 112G+ SerDes speed, especially short reach and low power designs.
• Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication, DDR5/LPDDR5; GDDR6/LPDDR6.
• Proficiency with analog design and verification tools (Virtuoso, Spectre, ADE).
• Knowledge of signal integrity improvement, noise reduction, and Multi-GHz low-jitter clock generation & distribution.
• Good understanding of analog layouts in FinFet and its effect on high-speed designs.
• Experienced in system level pre-tape out analog validation.
• Experienced in lab chip bring-up and debugging efforts.
• Strong communication skills.

Nice To Haves

• Experience with design D2D interface such as UCIe.
• Experience with 112G+ SerDes speed.
• Experience in Single-ended High Density Parallel Interface for Chip to Chip Communication.

Responsibilities

• Lead a team of analog design engineers.
• Interface with layout, verification, and application teams.
• Manage delivery of analog IP.
• Conduct architectural investigations and implementation for circuits.
• Perform design verification using industry standard tools.

Benefits

• Flexible time off.
• 401k.
• Year-end shutdown.
• Floating holidays.
• Paid time off to volunteer.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: Master's degree
• Number of Employees: 5,001-10,000 employees