Analog Engineer Intern - PhD

Marvell Technology-posted 3 months ago
$31 - $61/Yr
Intern
Santa Clara, CA
5,001-10,000 employees
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Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Analog Mixed-Signal Optical PHY (AMS-OPHY) Central Engineering unit delivers 10G-800G high-speed optical and electrical connectivity solutions to OEM’s for the networking and telecommunication markets. It’s PAM4-DSP based transceivers deliver a first-in class solution to present and future data throughput demands across multiple applications. Common applications for the AMS-OPHY products include long haul and metro, inter and intra-data center interconnects and 5G.

  • High speed analog to digital (ADC) or digital to analog (DAC) interface circuits
  • High speed ADC or DAC driver circuits
  • High speed clock conditioning circuits
  • Auxiliary circuits (i.e., biasing, reference generation)
  • Behavioral modeling to aid/facilitate the circuit design process
  • Calibration algorithms to mitigate circuit non-idealities
  • Model analysis/development for characterizing the impact of circuit performance at the system level
  • Candidate MUST be currently pursuing an MS/PhD (preferred) degree in EE or related technical field(s)
  • Candidate MUST have a deep and comprehensive understanding of analog integrated circuit fundamentals
  • Candidate MUST have a good understanding of signal processing fundamentals
  • Candidate MUST have experience with CAD tools and simulators such as Cadence Virtuoso and Spectre
  • Research or Major design project experience in data conversion (i.e., ADC’s & DAC’s) interfaces
  • Research or Major design project experience in high-speed analog front ends (i.e., CTLE’s, VGA’s, TAH/SAH’s)
  • Research or Major design project experience in clock conditioning circuits (i.e., PLL’s, DLL’s, PI’s)
  • Experience in behavioral modeling in Verilog-A and or System Verilog
  • Experience in C, Python and Matlab programming/modeling in a Unix type environment
  • Medical, dental and vision coverage
  • Perks and discount programs
  • Wellness & mental health support including coaching and therapy
  • Paid holidays
  • Paid volunteer days
  • Paid sick time
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