Qualcomm-posted 2 months ago
$176,300 - $264,500/Yr
Full-time • Senior
Santa Clara, CA
Computer and Electronic Product Manufacturing

As a AI/ML Design Verification Methodology Lead, will involve in developing and implementing verification strategies, methodologies, and environments to ensure the functionality, performance, and robustness of variety of Qualcomm WIFI, connectivity and IOT devices architectures. The successful candidate will also lead a team of verification engineers and collaborate closely with design, architecture, and software teams.

  • Define and drive AI/ML verification methodology.
  • Develop and enhance constrained-random verification environments using SystemVerilog and UVM.
  • Lead and mentor a team of verification engineers.
  • Collaborate cross-functionally with other teams.
  • Explore innovative DV methodologies (formal, simulation, and emulation strategies) to continuously push the quality and efficiency of test benches by adopting emerging techniques and tools.
  • Act as a technical point of contact to the different IP and SoC design teams.
  • Provide technical leadership through personal example, mentorship, and strong teamwork.
  • Over 5 years of ASIC/SoC verification experience, with at least 2 years in a leadership role.
  • Experience with various aspects of digital verification such as test automation, code and functional coverage, constraint randomization, system Verilog assertions, and performance.
  • Proven experience in verifying complex AI/ML hardware or high-performance compute cores.
  • Proficiency in System Verilog / UVM based verification skills, experience with assertions, and coverage-based verification methodology.
  • Experience with C/C++, assembly language.
  • Knowledge of low power design concepts and power management.
  • Strong communication and leadership skills.
  • Experience with AMBA bus protocols.
  • Experience with GLS, and scripting languages such as Perl, Python.
  • Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
  • 9+ years of ASIC design, verification, validation, integration, or related work experience.
  • 3 + years of experience with architecture and design tools.
  • 3 + years of experience with scripting tools and programming languages.
  • 3 + years of experience with design verification methods.
  • 2 + years of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).
  • Competitive annual discretionary bonus program.
  • Opportunity for annual RSU grants.
  • Comprehensive benefits package designed to support success at work, at home, and at play.
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