We are ready to hire an FPGA Engineer to join our Air and Missile Defense (AMDR) program working to develop and deploy the next generation AN/SPY-6 radar for the U.S. Navy. Our close-knit team is passionate about delivering the best product to the Navy to help protect our country. Imagine being part of the team that develops the technologies, products and services that help our nation’s heroes keep our nation safe. The work is important. The challenges are career-defining. The opportunity is waiting for you at GDMS as an FPGA Engineer. What You’ll Experience: Your Role: Leading and contributing to advanced FPGA design, development, debugging, and testing projects. Collaborating with a dynamic team on cutting-edge technologies and innovative solutions. Hands-on experience with industry-standard tools like AMD Vivado and simulation tools such as QuestaSim. Opportunities to tackle complex technical challenges and make a significant impact. A supportive and flexible work environment that fosters professional growth. Responsible for definition, design, verification, documentation, development, maintenance and debug of several classified FPGA (Field Programmable Gate Array) Determines architecture, system simulation and detailed design approach Defines module interfaces and all aspects of devise design and simulation Evaluates the process flow including but not limited to high level design, synthesis, place and route, timing and power utilization Creates test and simulation plans that establish functional criteria Verifies test results and analyzes performance May also review vendor capabilities, foundry technologies, device libraries and simulation tools Participates in the improvement of the ASIC/FPGA organizational processes Review, modify and debug existing RTL code and cores in an effort to find, understand and repair complex problems reports at several different Radar test sites Participate in a fast paced environment that supports several geographically dispersed Radar test sites Participate in daily customer call in an effort to provide suggestions to help resolve and diagnosis problems that may be difficult to recreate in simulation or with test hardware available in our labs Supports the generation of technical engineering products by using the appropriate standards, processes, procedures, and tools throughout the ASIC/FPGA development life cycle Some Travel may be required
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Job Type
Full-time
Career Level
Mid Level