Advanced Defect Modeling and Testing (Technical Manager) (7101)

TSMC • San Jose, CA

94d • $152,500 - $244,000

About The Position

We are seeking an experienced engineer to join our team researching advanced defect modeling, testing, screening, and analysis for next-generation semiconductor processes and 3D packaging technologies. This role is strategically critical for TSMC: it represents a multi-year journey to pioneer new approaches to defect modeling in advanced packaging. Defect modeling in this space is still an emerging discipline, with global leaders actively defining the standards. This position provides a unique opportunity to keep TSMC at the forefront of innovation and shape the methodologies that will guide the industry. The successful candidate will develop methodologies and tools to model and simulate defects, assess their impact on performance, optimize testing strategies, and innovate beyond the limitations of current testing instruments. This engineer will collaborate across design, process, test, and reliability functions to ensure the functionality and yield of advanced 2.5D/3D packaging technologies.

Requirements

• Master’s or Ph.D. in Computer Engineering, Semiconductor Physics, or a related field.
• At least 15+ years of expertise in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices, including 2D and 3D structures.
• Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes.
• Programming or scripting skills (Python, Perl, C++) for automation and data analysis.
• Deep understanding of defect physics, testing/probing structures, and their impact on defect detection, characterization, and yield learning in advanced process nodes and 3D packaging.
• Familiarity with thermal and mechanical considerations in 3D integration.
• Demonstrated contributions through patents, publications, or conference presentations in defect modeling, reliability, or advanced packaging.

Nice To Haves

• Experience with AI/ML for defect prediction.

Responsibilities

• Develop defect models for 2D structures (standard cells, FEOL/MEOL/BEOL layers) and 3D structures such as TSVs, interconnects, hybrid bonding, and chip stacking.
• Perform root-cause analyses of electrical, mechanical, and thermal defects in advanced packages and address them using design-for-test methods.
• Conduct SPICE simulations to evaluate circuit behavior under defect conditions and identify failure scenarios.
• Use EDA ATPG tools (or develop internal methods) to generate defect-oriented test patterns.
• Assess the influence of probing techniques and test structure designs on defect detection and reliability learning.
• Develop and implement methodologies leveraging test/probe structures to monitor process variations and enhance yield.
• Implement advanced test methodologies for defect detection at both chip and package levels.
• Stay updated on evolving technologies and defect mechanisms in semiconductor manufacturing.
• Contribute to patents and publications in leading conferences and journals.
• Collaborate across design, process, and manufacturing teams.

Benefits

• Market competitive pay
• Allowances
• Bonuses
• Comprehensive benefits
• Extensive development opportunities and programs

What This Job Offers

• Education Level: Ph.D. or professional degree
• Number of Employees: 5,001-10,000 employees