Advanced ASIC RTL to Netlist Physical Design Lead (Teradyne, North Reading, MA)
About The Position
We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team – one that makes better decisions, drives innovation and delivers better business results.Opportunity OverviewTeradyne is seeking an experienced Physical Design Lead to join our Silicon Technology Engineering (STE) organization within the Digital ASIC Group. This team develops advanced-node, large-scale mixed-signal ASICs that are foundational to Teradyne’s next-generation SoC and memory test platforms. In this highly visible technical leadership role, you will own RTL-to-GDSII execution for complex ASICs, working closely with digital and analog designers, product architects, and chip leads. You will guide physical design architecture, mentor engineers, and play a critical role in delivering high-quality, first-pass silicon at advanced process nodes.
Requirements
- 10+ years of hands-on ASIC physical design experience, including leadership of large or complex PD projects
- Proven experience at advanced technology nodes (16nm and below)
- Deep expertise in RTL-to-GDSII flows and timing closure
- Strong understanding of STA, constraints development, and signoff methodologies
- Experience integrating high-speed and complex IP (e.g., PCIe, DDR5/DDR6, UFS, SerDes)
- Proficiency with industry-standard EDA tools (Cadence preferred)
- Strong scripting and automation skills using Tcl, Python, and/or Make
- Ability to lead technically, communicate clearly, and collaborate across disciplines
- BS or MS in Electrical Engineering (or equivalent practical experience)
Responsibilities
- Lead and mentor a team of physical design engineers across the full project lifecycle
- Lead high-level physical design planning and define PD architecture in collaboration with chip and system architects
- Develop and own chip floorplans, timing budgets, power estimates, and pin planning
- Partner with design teams to develop high-quality SDC constraints
- Drive RTL-to-netlist activities including synthesis, logical equivalence checking (LEC), clock domain crossing checks (CDC), and static timing analysis (STA)
- Support hands-on place-and-route (P&R) for critical and high-speed blocks
- Collaborate with a backend physical design house to support P&R execution, debug flow or implementation issues, and meet schedule and quality goals
- Integrate complex IP such as PCIe, DDR5/DDR6, UFS, and SerDes
- Ensure robust signoff closure including DRC/LVS and EM/IR analysis
- Develop, enhance, and maintain physical design tool flows and automation
Benefits
- Competitive compensation, benefits, and career growth opportunities
- Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.
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What This Job Offers
Job Type
Full-time
Career Level
Mid Level
Number of Employees
1,001-5,000 employees
