3D Stacked Memory Architect

Micron Technology • San Jose, CA

6d

About The Position

Our vision is to transform how the world uses information to enrich life for all. Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever. We build the memory technologies that power the world’s most demanding platforms. Our team works at the intersection of silicon, packaging, and systems, pushing the limits of bandwidth, efficiency, and reliability. If you want to shape where memory goes next, this is the place to do it. This role sits at the center of our next-generation stacked memory strategy. As a Senior Memory Architect, you will define architectures that span die, stack, package, and system, and influence how customers and platforms adopt them. You will lead through technical depth, guide major architectural decisions, and help translate bold ideas into production reality.

Requirements

• Bachelor’s degree or equivalent practical experience in Electrical Engineering, Computer Engineering, Computer Science, or a related field
• Extensive industry experience in stacked memory, 3D integration, advanced packaging, or high-performance semiconductor architecture
• Deep hands-on expertise in high-speed I/O, TSV-based stacking, power delivery, thermals, and signal integrity
• Proven ability to translate system-level requirements into memory and package architecture
• Demonstrated technical leadership across teams and complex architectural decisions

Nice To Haves

• Master’s degree or PhD in Electrical Engineering or a related technical field
• Recognized expertise in stacked memory or advanced packaging, internally or externally
• Experience influencing tier-1 customers, platform architects, or industry standards
• Track record of architectural innovations shipped in production silicon or platforms
• Experience mentoring senior engineers or architects

Responsibilities

• Define next-generation 3D stacked memory architectures spanning bandwidth, capacity, power efficiency, and RAS
• Lead die-to-system co-optimization across memory die, PHY, TSVs, bonding, packaging, and system integration
• Architect stack-aware RAS, telemetry, and reliability mechanisms for high-density memory systems
• Drive long-range technology strategy for stacked memory and advanced packaging
• Engage deeply with customers, platform partners, and standards bodies to influence system and ecosystem direction

Benefits

• medical
• dental
• vision plans
• benefit programs that help protect your income if you are unable to work due to illness or injury
• paid family leave
• a robust paid time-off program
• paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level
• Number of Employees: 5,001-10,000 employees