3.5D Packaging For Datacenter GPU

Advanced Micro Devices, Inc•Austin, TX

2d•Hybrid

About The Position

At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: Execute end-to-end productization of industry’s most advanced chiplet packaging architectures for high performance computing applications. Lead product scoping, development, and execution to high volume manufacturing, meeting critical program requirements for performance, cost, schedule, reliability, and quality. THE PERSON: Strong organizational skill to coordinate heterogeneous integration packaging solutions with advanced packaging technologies, delivering project milestones across internal and external teams for mature product readiness and robust high volume manufacturing. Working knowledge of advanced 2.5D/3D package manufacturing and materials preferred.

Requirements

10 + years of semi-conductor packaging experience
Experience and working knowledge with 2.5D/3D advanced packaging technologies such as WLFO, SoIC, CoWoS, InFO, IVR, and other chiplet/SiP architectures.
Knowledge of surface mount technology (SMT) and process development for advanced system assembly.
In depth experience with product package qualification including process characterization, Product Life Management, Chip-Package Interactions, Test-Package Interactions, environmental testing of component and board level reliability, and failure analysis techniques.
Experience with wafer bumping, wafer sorting, package assembly, substrate technology, thermal interface materials, adhesives and underfills, package testing, package socketing, and associated metrologies.
Knowledge in substrate design, manufacturing, and assembly interactions.
Strong problem solving, communication, organizational, interpersonal, and presentation skills.

Responsibilities

Coordinate package design and assembly of advanced 2.5D/3D packages, driving material and BOM choices, body sizes, manufacturability, and package constructions to achieve acceptable DFM requirements.
Coordinate with SoC architects, silicon design, and product teams to recommend the optimum package solutions to meet electrical, mechanical, thermal, and system level requirements.
Interface closely with AMD’s manufacturing and material partners to productize advanced packaging solutions from concept to NPI. Prototyping to mass production phases with acceptable sustaining yields.
Support and collaborate with customers to ensure that AMD packages/products can meet their quality, reliability, system, and operational needs.
Perform product risk assessment with mitigation plans and establishing best known processes methodology to ensure robust package quality, reliability, and manufacturing yield.
Lead and perform DOE definition for process optimization and material screening to enable new product concepts with optimum yield targets.
Drive design solutions to address SI/PI, reliability, and thermal challenges associated with package design and materials.