SoC Physical Design Engineer

Intel-posted 8 months ago
$139,710 - $197,230/Yr
Full-time • Mid Level
Hybrid • Hillsboro, OR
Computer and Electronic Product Manufacturing
Resume
Match Score
Upload and Match ResumeTrack Jobs with Teal

We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.

  • Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
  • Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools.
  • Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF.
  • Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking.
  • Analyzes results and makes recommendations to fix violations for current and future product architecture.
  • Participating in the development and improvement of physical design methodologies and flow automation.
  • Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs.
  • Bachelor's degree in electrical engineering, Computer Engineering or related field with 5+ years of relevant experience OR Master's degree Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience.
  • Relevant experience in Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.
  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.
  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.
  • 6+ years of experience in physical design using industry EDA tools.
  • 7+ years of experience in backend design and/or integration.
  • Product development and delivery on leading edge process nodes.
  • Experience in Python/Perl/TCL programming languages.
  • Competitive pay
  • Stock options
  • Bonuses
  • Health benefits
  • Retirement plans
  • Vacation
Track Jobs with Teal

Job Search Resources

•
Resume Builder
•
Resume Examples
•
Cover Letter Examples

Tools

Career Hubs

Guides

Company

© 2024 Teal Labs, Inc
Privacy PolicyTerms of Service