Engineer, Senior|6288 Engineer, Senior|6288

ACL Digital • Santa Clara, CA

298d

About The Position

The position requires strong expertise in Static Timing Analysis (STA) and a solid understanding of AOCV/POCV concepts, Clock Tree Synthesis (CTS), and constraints debugging. The candidate should have hands-on experience with STA tools, particularly PrimeTime, and should be capable of driving timing convergence at both the Chip-level and Hard-Macro level. In-depth knowledge of cross-talk noise, Signal Integrity, Layout Parasitic Extraction, and feed-through handling is essential. Familiarity with ASIC back-end design flows, methods, and tools such as ICC2 and Innovus is also required. Proficiency in scripting languages like TCL, Perl, and Python is necessary, along with a basic understanding of device physics. Knowledge of Physical Design (PD) tools and flow is considered a plus.

Requirements

• Strong expertise in STA timing analysis basics.
• Hands-on experience with STA tools, specifically PrimeTime.
• Experience in driving timing convergence at Chip-level and Hard-Macro level.
• In-depth knowledge of cross-talk noise and Signal Integrity.
• Familiarity with Layout Parasitic Extraction and feed-through handling.
• Knowledge of ASIC back-end design flows and tools (ICC2, Innovus).
• Proficient in scripting languages such as TCL, Perl, and Python.
• Basic knowledge of device physics.

Nice To Haves

• Knowledge of PD tools and flow.

Responsibilities

• Perform STA timing analysis and ensure timing closure.
• Drive timing convergence at Chip-level and Hard-Macro level.
• Debug constraints and ensure proper implementation.
• Analyze cross-talk noise and Signal Integrity issues.
• Handle Layout Parasitic Extraction and feed-through challenges.
• Utilize STA tools like PrimeTime effectively.
• Collaborate with teams on ASIC back-end design flows and tools.

What This Job Offers

• Industry: Professional, Scientific, and Technical Services
• Number of Employees: 1,001-5,000 employees