AMD-posted 8 months ago
$191,040 - $286,560/Yr
Santa Clara, CA
Computer and Electronic Product Manufacturing

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance. The team: AMD's NTSG - Network Technologies Solutions Group is a leading provider of data center networking technology. The distributed services platform will expand AMD's data center product portfolio with a high-performance data processing unit (DPU) and software stack that are already deployed at scale across cloud and enterprise customers including Goldman Sachs, IBM Cloud, Microsoft Azure and Oracle. We are hiring a ASIC Verification Engineer to help contribute to rapidly expanding and innovative chip designs in both 7nm and 5nm process technologies. We are developing cutting-edge domain specific processors for the IAAS and smart-switch markets that leverage the P4 programming language to provide software-defined features and scale but with hard-wired performance attributes. Applications include advanced PCIe, networking, storage, and security virtualization services for both the public and private cloud markets.

  • Developing and executing test plans for Unit/IP/Subsystem/SOC level verification
  • System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points
  • Identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills
  • Solid knowledge and understanding of Computer Architecture
  • Experience developing and executing test plans for Unit/IP/Subsystem/SOC level verification
  • Experience in System Verilog test bench development including stimulus, checkers, transactors/BFMs, assertions and cover points
  • Experience identifying bugs in architecture, functionality and performance with strong overall debug and analytical skills
  • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy/DVE)
  • Excellent debugging and problem-solving skills
  • Languages and tools: UVM, System Verilog, C or C++
  • System Verilog simulators and waveform debuggers
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