Sr. Staff ASIC Verification Engineer

Tensordyne•Sunnyvale, CA

4d•Hybrid

About The Position

As a senior member of Tensordyne’s ASIC team, you will lead all phases of ASIC verification and will be responsible for the pre-silicon correctness of Tensordyne’s next-generation family of processors for generative AI inference acceleration. This ASIC’s design closely couples novel computational accelerator units with 3rd-party SoC IP blocks to deliver the high-performance multi-chip silicon solutions that are at the heart of Tensordyne’s vertically integrated, generative AI inference acceleration systems for data centers.

Requirements

15+ years of ASIC verification experience - having taken multiple chips through the entire cycle of verification and post silicon validation
Expert in System Verilog, UVM, Constraint Randomization, Functional Coverage.
Experience in C/C++ or System-C
Deep understanding of object oriented programming principles, constrained random stimulus, and coverage driven verification approach.
Verification experience of high-speed interfaces (PCIe, Ethernet, DDR/HBM, SerDes, etc.)
Scripting experience (Python, Perl, TCL, shell programming) highly-desirable.
Interest to explore AI architectures for convolution, transformer and other kinds of workloads
Self-starter and highly-motivated to work in a dynamic start-up environment.
B.S. (M.S. preferred) degree in Electrical or Computer engineering (or similar field).

Responsibilities

Working closely with design engineers to stay abreast of the specification and implementation of ASIC blocks.
Developing comprehensive test and coverage strategies.
Implementing the verification environment and tests using object-oriented tools, in particular SystemVerilog and UVM.
Handling bug tracking and coverage convergence.
Developing scripts and methodologies for the front-end ASIC flow.
Ensure the pre-silicon correctness and quality of a multi-million gate ASIC that integrates computational accelerators and 3rd-party SoC IP blocks.
SoC/Subsystem verification of embedded CPUs such as ARM/RISC-V and interconnect subsystem (including C and assembly diag validation).
Lead verification planning from architecture through tapeout.
Develop block-level, sub-system and full-chip verification environment and tests to implement test plans.
Establish reusable verification methodologies and frameworks - scale testbenches to subsystem and full chip environments.
Work closely with design and architecture teams to understand the functional and performance goals of the design; and work together to make the design-under-test work under all specified circumstances.
Triage and debug functional and performance issues with the design-under-test.
Drive verification signoff criteria and quality metrics - handle bug tracking, coverage convergence, regression failures.
Mentor and technically guide verification engineers helping them through test planning and verification closure.
Perform diagnostic and post-silicon validation tests in the lab.