Silicon Product Engineering Graduate Intern

Intel Corporation•Hillsboro, OR

1d•$89,200 - $120,700•Onsite

About The Position

Support development and maintenance of assembly design rules that addresses the capabilities and constraints of advanced silicon packaging and heterogeneous integration. Contribute to package assembly design kit by creating and evaluating test cases for different assembly configurations. Evaluate constraints arising from multidie integration, including flipchip, substrate routing, bump placements, and interconnect patterns, ensuring compliance with documented assembly rules. Interpret design rule impacts on manufacturability, yield, and system-level integration requirements. Assist in reviewing bump layouts and propose corrections across a design life cycle. Prepare reports summarizing rule checks, violations, and recommendations, helping maintain an up to date, well organized assembly rule knowledge base.

Requirements

Currently pursuing a Masters or PhD in Electrical Engineering, Computer Engineering, or a related field with a focus on semiconductor devices or silicon testing.
3+ months experience with packaging assembly design.
Experience with root cause analysis and problem solving in a technical environment.
Familiarity with technical documentation and communication of engineering results.

Nice To Haves

Demonstrated ability to collaborate effectively with cross-functional teams in a research or engineering environment.
Knowledge of design for debug (DFD) principles and their applications in silicon validation.
Strong interest in continuous learning and improvement within the semiconductor domain.
Passion for making meaningful contributions to innovative technologies and products.

Responsibilities

Assist in the validation, debugging, and testing of silicon products, from initial bring-up to high-volume manufacturing.
Collaborate with cross-functional teams to resolve engineering challenges, optimize product performance, and improve yield and reliability.
Learn and apply principles of design for test (DFT), manufacturing (DFM), and debugging techniques to support product lifecycle and qualification.
Conduct root cause analysis and problem-solving to identify and address engineering issues effectively.
Contribute to the development and optimization of test engineering processes, tools, and documentation.
Support the analysis and optimization of power and performance metrics for silicon products.
Continuously build technical knowledge and skills through hands-on experience and collaborative projects.