Senior Design Verification Engineer

NXP Semiconductors•Austin, TX

22h•Onsite

About The Position

Advanced Chip Engineering's Digital IP team defines and develops components for a wide range of products, including automotive microprocessors, application processors, microcontrollers, and networking. The Austin Digital IP team develops components for DDR, display controller, high-speed serial links, DMAs, cores, memory controllers, and interconnect. This role involves defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications). The engineer will create intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases. Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan is also a key responsibility. The role includes writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness, as well as developing and maintaining portions of a verification environment including scripts and Make files. Debugging failing testcases to determine the source of failure (tool, testcase, checker, verilog RTL) and tracking resolution is crucial. Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage is required. Performing assertion-based formal verification of blocks and IPs to ensure they meet requirements is also part of the job. Digital IP Functional Verification involves learning precise operating expectations for digital designs containing constant new and innovative features, and implementing pre-silicon simulations to test, find and fix every possible bug in the design, in order to achieve the highest level of quality. Challenges will include understanding the expected operation of new and innovative features, predicting where bugs are most likely to be hiding in the design, and implementing the most efficient and robust solutions to find and fix design bugs against schedules and deadlines for the products. Keen engineering problem solving skills and a mind for seeking innovative solutions to reduce effort while increasing productivity and automation are all areas that are highly valuable in Functional Verification. The design verification engineer will work with other members of the architecture, design and verification teams to verify IP designed in-house or purchased from 3rd party vendors.

Requirements

Minimum BSEE/BSCE/BSCS
Minimum 4 years of experience in IP or SoC design or verification
Hands on experience in using AI/ML tools for workflow and productivity improvements
Verilog, SystemVerilog, UVM coding skills required
Verification skills (test planning, testcase, testbench, simulation, debug) required
Ability to work independently and in small teams without close supervision required

Nice To Haves

MSEE/MSCE/MSCS a plus
Other programming skills (Python, C/C++, Perl, TCL, etc.) a plus
Design skills (design documentation, RTL coding, synthesis, static and formal checkers, etc.) a plus
Knowledge of ARM AMBA® protocols a plus

Responsibilities

Defining and writing IP verification plans based on requirements documents (industry standards, product requirements, IP architecture and IP implementation specifications)
Creating intelligent stimulus in System Verilog (UVM), random test scenarios, algorithmic and directed testcases
Defining and writing System Verilog Assertion (SVA) cover properties to match the verification plan
Writing System Verilog (UVM) monitors, drivers, response checkers and SVAs for correctness
Developing and maintaining portions of a verification environment including scripts and Make files
Debugging failing testcases to determine source of failure (tool, testcase, checker, verilog RTL) and track resolution
Collecting code and functional coverage results from random simulations, and analyzing uncovered events to determine additional test scenarios needed to achieve 100% coverage
Performing assertion-based formal verification of blocks and IPs to ensure they meet requirements