Senior ASIC Physical Design Engineer

$150,000 - $180,000/Yr

Capgemini Holding - Santa Clara, CA

Full-time - Senior

Santa Clara, CA

Professional, Scientific, and Technical Services

About the position

Capgemini Engineering is seeking a Senior ASIC Physical Design Engineer to join our team in Santa Clara, CA. This hybrid position involves working on chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration, and ECO generation. The ideal candidate will have expertise in timing closure (STA) of high frequency blocks and experience handling blocks with high instance counts and complex designs, specifically those with over 1 million instances and clock frequencies around 1 GHz. The role requires knowledge of low power implementation, signoff closure, and physical verification at both block and chip levels. Candidates should be proficient in layout edit techniques and familiar with tools such as Synopsys Fusion Compiler, ICC/ICC2, PTSi, and Cadence EDA Tool Suite.

Responsibilities

• Chip level floor planning, partitioning, timing budget generation, power planning, top-level PnR, CTS, block integration and ECO generation.
• Expertise in timing closure (STA) of high frequency blocks.
• Handling blocks of high instance counts and complex designs - 1M+ instances and clock frequencies about 1 GHz.
• Experience with low power implementation and signoff, power gating, multiple voltage rails, UPF knowledge.
• Experience in Block-level and Full-chip integration.
• Knowledge of signoff closure - Timing with SI and OCV, Power, IR and Physical Verification at both block and chip level.
• Understanding constraints and fixing design/timing techniques.
• Block level implementation from netlist to GDS.
• Understanding SI prevention, fixing methodology and implementation.
• Proficient in layout edit techniques.
• Proficient in Synopsys Fusion Compiler, ICC/ICC2, PTSi, and Cadence EDA Tool Suite.
• Experience in Design Automation and UNIX system.
• Experience in Tcl/Tk, PERL, Python is a plus.

Requirements

• Must possess 8+ years of hands-on experience in handling block/chip level implementation from Netlist to GDSII.
• Must possess hands on experience in timing closure and physical verification closure.
• Must have handled blocks of sizes 1M instances and above at frequencies higher than 1GHz.
• Experience in handling lower tech nodes that include 3nm, 5nm, 7nm, 10nm, 16nm, etc.
• Must have hands on tape-out experience in lower tech nodes in any of the tools mentioned such ICC/ICC2, Fusion Compiler or Cadence APR tools.
• Must have the ability to think on the spot for quick solutions and work-around at the time of tape-out to hit the schedule on time.
• Must possess excellent scripting skills - TCL or Perl or Python.
• Experience in Synthesis and Formal is a plus.
• Excellent verbal and written communication skills are required.
• Must possess excellent debug skills, analytical skills, and the ability to work independently.
• Must be highly motivated and possess excellent team spirit.

Nice-to-haves

• Experience in Synthesis and Formal is a plus.
• Experience in Tcl/Tk, PERL, Python is a plus.

Benefits

• Flexible work.
• Healthcare including dental, vision, mental health, and well-being programs.
• Financial well-being programs such as 401(k) and Employee Share Ownership Plan.
• Paid time off and paid holidays.
• Paid parental leave.
• Family building benefits like adoption assistance, surrogacy, and cryopreservation.
• Social well-being benefits like subsidized back-up child/elder care and tutoring.
• Mentoring, coaching and learning programs.
• Employee Resource Groups.
• Disaster Relief.